Principal Digital Verification Engineer

About the role

The Principal Digital Verification Engineer will lead verification activities for one or more sub‑modules, including IPs and testbenches, within NXP's semiconductor projects. You will work closely with architects, designers and the DV team to ensure a robust verification strategy and successful delivery.

Key responsibilities

• Own and drive verification of assigned sub‑modules, creating and maintaining testbenches and verification IPs.
• Review subsystem requirements and design specifications for each functional or technology increment.
• Define an integrated verification strategy with architects and discipline leads, breaking it down into tasks and effort estimates.
• Document metrics, methodology and verification progress, producing specs and reports for each project phase.
• Collaborate with hardware, software and system engineers to analyse and resolve issues quickly.
• Contribute to DV process improvements and stay updated on the latest verification tools and methodologies.

Required profile

• Master’s or PhD in Electrical/Electronic Engineering, Computer Science or related field.
• At least eight years of professional experience in digital design and verification.
• SystemVerilog and UVM methodology certifications from EDA vendors.
• Familiarity with ASIC/SoC design flow and processes.
• Strong English communication skills, both spoken and written.

Required skills

• Advanced knowledge of Verilog, SystemVerilog (VHDL a plus).
• Proven experience designing testbenches using UVM.
• Metric‑driven verification, functional and code coverage, directed and constrained‑random testing.
• Formal verification techniques and assertions.
• Scripting languages: bash/tcsh, Tcl, Python, C.
• Version control systems: SVN, GIT, Clearcase.

What we offer

• Competitive market‑based compensation.
• Home‑office options and flexible working time.
• Meal benefits and other employee perks.